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wiki:projects:vnarefit:diag_details [2018/02/01 18:09]
nats [Mixer]
wiki:projects:vnarefit:diag_details [2019/03/26 16:43] (current)
nats [Analog FrontEnd]
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 ===== Digital Part ===== ===== Digital Part =====
-This part of the project is not really new. We have a Spartan6 LX9 in TQFP (certainly replaced by a Spartan 7 in next version) and a FT2232H to grab data on the USB2 bus. The FT2232H is used in Synchronous FT245 mode. The details of the FPGA internal design can be found [[wiki:​projects:​vnarefit:​fpga_diag|here]].+This part of the project is not really new. We have a Spartan6 LX9 in TQFP (certainly replaced by a Spartan 7 in next version) and a FT2232H to grab data on the USB2 bus.  
 +The FT2232H is used in Synchronous FT245 mode. The details of the FPGA internal design can be found [[wiki:​projects:​vnarefit:​fpga_diag|here]].
  
 ===== RF Part ===== ===== RF Part =====
 ==== PLL ==== ==== PLL ====
 +The PLL board will be separated on a mezzanine to reduce the cost of the PCB (we need a RF substrate for this one where the digital part doesn'​t need it).
 +
 Since the board is meant to be used in setup from 2 to 12GHz the component choice is limited. Analog Devices has some niffty PLL in the catalog. This project use two of them: Since the board is meant to be used in setup from 2 to 12GHz the component choice is limited. Analog Devices has some niffty PLL in the catalog. This project use two of them:
   - [[http://​www.analog.com/​en/​products/​rf-microwave/​pll-synth/​plls-w-integrated-vcos/​adf4355.html|ADF4355]]:​ This one goes from 54 to 6800MHz and is used to generate the two LO.   - [[http://​www.analog.com/​en/​products/​rf-microwave/​pll-synth/​plls-w-integrated-vcos/​adf4355.html|ADF4355]]:​ This one goes from 54 to 6800MHz and is used to generate the two LO.
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-==== Mixer ==== +==== Analog FrontEnd ​==== 
-The input stage is based on [[http://​www.linear.com/​|Linear Tech]] Mixer: +The Analog Front End is on a separated board in the V2, it was necessary to correct for some problem encountered in the V1. The AFE board is now embedding two mixer, a splitter for the LO 
-  - [[http://​www.linear.com/​product/​LTC5548|LTC5548]]:​ This mixer goes from 2 to 14GHz LO/RF ! And 0 to 6GHz IF. The LO has a doubler integrated (can be activated independantly). ​This mixer suit perfectly ​the needs, please note if you need single ended output over 500MHz the LTC5549 ​is integrating an output balun !+and a baseband filter. Since we want to also make second port measure we need two port usable simultaneously,​ the V1 showed that being able to measure the second port is a must have for 
 +a good calibration. Each AFE has two port, one for the measure port and the other one for reference ! So we need two AFE which can be arranged to have 2 or 3 port and a reference. 
 + 
 +{{wiki:​projects:​vnarefit:​afe_vna_cut.jpg?​250}} 
 + 
 +The input stage is based on [[http://​www.linear.com/​|Linear Tech]] Mixer: 
 +  - [[http://​www.linear.com/​product/​LTC5548|LTC5548]]:​ This mixer goes from 2 to 14GHz LO/RF ! And 0 to 6GHz IF. The LO has a doubler integrated (can be activated independantly). 
 + 
 +The baseband amplifier + filter is an [[https://​www.analog.com/​en/​products/​adrf6516.html|ADRF6516]] and the LO is distributed by [[https://​www.minicircuits.com/​WebStore/​dashboard.html?​model=EP2C%2B|EP2C+]]. 
 +The AFE is made to be connected using a SATA cable to the baseband.
  
-The differential output directly goes to an [[http://​www.analog.com/​en/​products/​amplifiers/​adc-drivers/​fully-differential-amplifiers/​ada4940-1.html|ADA4940-1]] with MFB topology filter. The filter is designed to be a 1MHz Low-Pass with an in-band gain of about 3 (to compensate for the mixer loss). An Input of 0dBm should be just on the range limit of the ADC. Giving a theorical 96dB dynamic range from -96 to 0dBm.+{{wiki:projects:​vnarefit:​afe_vna_diagramm.jpg?400}}
  
-//In the first prototype one of the two path has a Mini-Circuit splitter and a Log Detector to measure the signal power but this feature will be removed and the power will be computed in the FPGA.// 
wiki/projects/vnarefit/diag_details.1517504976.txt.gz · Last modified: 2018/02/01 18:09 by nats