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RF Part

Analog FrontEnd

The Analog Front End is on a separated board in the V2, it was necessary to correct for some problem encountered in the V1. The AFE board is now embedding two mixer, a splitter for the LO and a baseband filter. Since we want to also make second port measure we need two port usable simultaneously, the V1 showed that being able to measure the second port is a must have for a good calibration. Each AFE has two port, one for the measure port and the other one for reference ! So we need two AFE which can be arranged to have 2 or 3 port and a reference.


The input stage is based on 2 Linear Tech Mixer:

  1. LTC5548: This mixer goes from 2 to 14GHz LO/RF ! And 0 to 6GHz IF. The LO has a doubler integrated (can be activated independantly).

The baseband amplifier + filter is an ADRF6516 and the LO is distributed by a EP2C+. The AFE is made to be connected using a SATA cable to the baseband.



The PLL board will be separated on a mezzanine to reduce the cost of the PCB (we need a RF substrate for this one where the digital part doesn't need it). I still need to design that one.

Since the board is meant to be used in setup from 2 to 12GHz the component choice is limited. Analog Devices has some niffty PLL in the catalog. This project use two of them:

  1. ADF4355: This one goes from 54 to 6800MHz and is used to generate the two LO.
  2. ADF5355: This one goes from 54 to 13600MHz and is used to generate the Sweep test signal.

These two PLLs are configured by the an SPI link coming from the FPGA, and parameters will be calculated on the ARM part of the Zynq.

The use of ADF4355 as the LO generator is made possible by the integrated LO Doubler present in the chosen mixer.

Digital Part

I wanted to use a more integrated solution for the second version, I switched for a Zynq. After considering doing my own board, the conclusion was it would be a loss of time and money. A lot of Zynq based SOM are available between 100 and 500$ making a 10 layers board with DDR and all other components would easily reach an higher price.

Since I have a uZed from Avnet I decided to use it.

The internal design will be based (subject to change) on:

  • One AXI Lite interface to configure all the device, mainly using SPI, I2C and Shift Register
  • One or Two AXI HP for the ADC Sample, at first there will be two of them to handle the two ADC but I plan to implement a lot of preprocessing in FPGA and having only one stream of data reaching the PS

Current Status: Linux Running and able to configure devices from Linux (using devmem).


wiki/projects/vnarefit/diag_details.txt · Last modified: 2019/07/03 23:19 by nats